Computing devices use memory devices to store data and code for a processor to execute its operations. As the memory devices decrease in size and increase in density, they experience more errors during processing, referred to as yield issues. Thus, memory devices experience increasing bit failures, even with modern processing techniques. To mitigate bit failures, modern memory provide internal error correction mechanisms, such as ECC (error correction codes). The memory devices generate the ECC data internally, and use the ECC data internally at the memory devices. The internal error correction within a memory device can be in addition to whatever system-wide error correction or error mitigation used in data exchanges between the memory devices and the memory controllers. It will be understood that the application of ECC within a memory device requires additional logic to compute the ECC, and to apply it to correct data bits. It will also be understood that the application of ECC internal to a memory device requires the ECC to be computed and applied in real time as data is exchanged with a memory controller or other component external to the memory device. Such realtime requirements can introduce delays into the data exchanges.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.